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On the current exercise sheet, we need to fill out the state of a reservation station of size 5 after specific clock cycles (2, 5, 14, 16) for the given program code:

    1               addi  r1, r0, 5
    2               muli  r2, r1, 5
    3               addi  r3, r2, 1
    4               add   r4, r2, r2
    5               div   r5, r4, r3

According to the task, there's a decode, execution and writeback phase. Decode and writeback phase take 1 clock cycle each. The execution phase can be performed on two functional units (the first providing SUB and ADD in 2 clock cycles and the second one providing all ALU operations in 10 clock cycles).

For filling out the table we're not sure, whether the decode stage happens completely before any instruction is passed to the execution stage (i.e. the table is being filled completely within the 5 clock cycles) or wether the first instruction can be executed directly after it is written to the reservation station? 

in * TF "Emb. Sys. and Rob." by (800 points)

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Since it is a pipeline, I think that the decode, execute, and writeback stages work in parallel, i.e., while instruction k is decoded, instruction k+j may be sent to an execution unit, and  yet another instruction's execution may be finished by the execution phase. Any instruction first has to be decoded in a cycle, and after that, it could be executed (if operands and execution units are available) from the next cycle on.
by (166k points)
Right, not decoding and executing in parallel would let possible parallelism go to waste.

For this exercise however, I will accept both variants as correct submissions, since the dependency-based (and parallel) execution is the core principle we want you to learn here.
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