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I've got some questions regarding the implementation of Dynamic Scheduling, i.e. what happens in which pipeline stage. I am referring to slides 73-85.

If I got everything right, IF and ID are responsible for filling the tables (RSV, ROB) and also for updating the forward references. EX is responsible for emptying the RSV, i.e. executing the instructions in data flow order (and waiting for the FUs to become ready if needed) and the WB stage is responsible for emptying the reorder buffer in program order.

Two main questions erose: first of all, what exactly is the difference between IF and ID here? What does IF what the ID does not and vice versa? I can not exactly draw that line by myself. Second of all, there should also be a MA stage, shouldn't it? Does the MA stage have any special tasks in terms of dynamic scheduling?

Thanks in advance for any responses.

Best regards
Marvin Ballat
in * TF "Emb. Sys. and Rob." by (1.2k points)

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In general, IF fetches instructions from the program memory and updates the PC (if that is not done elsewhere like in WB). In case of dynamic scheduling, it must possibly wait until there is space available in the RSV and the ROB since otherwise a fetched instruction cannot be handed over. If the space is available, the instruction can be handed over to the ID phase that will decode it, get the operands or forward references for the latter and puts the information in the RSV and the ROB. The differences between IF and ID may become a bit blurred here, however, since one wishes to balance the work between the pipeline stages also.

About the MA stage: There could be a couple of stages MA[1], MA[2],... MA[n] for instance if the processor would have 15 pipeline stages or more, that is not uncommon simply to model the delay of the memory access accordingly in terms of pipeline cycles. However, the memory access of one thread still has to be done in order in that the MA stage will empty the load/store buffer that is filled by the WB phase that empties the ROB. Actually MA and WB work somehow in parallel, since the WB has to take load/store instruction from the head of the ROB and puts them in the load/store buffer. Store operations are dealt there without further interactions, but load instructions deliver a value that is the be written back to a register by the WB phase (and that again has to be done in order which may cause some back pressure to other instructions waiting in the ROB).

The pipeline phases are not that strictly separated here, and actually they are also not that precisely define in pipelined processors. The typical stages IF, ID, EX, MA, WB date back to the first RISC processors and reflect the major tasks that have to be done. However, processors with more than five pipeline stages (i.e., essentially all processors today) have more stages that take care of the different tasks that have to be done so that the overall work is balance among the pipeline stages. Hence, don't think too much about what is the task of one phase instead of another one, that may differ here and there.

Also while the lecture discusses one particular implementation of dynamic scheduling, it may also be organized differently. For instance, many processors have one RSV per execution unit that buffers the instructions to be executed there.   

rm noch weiter besteht, bleibt abzuwarten. Ich bin der Meinung dass wir genauso weitermachen sollen, bis eine Entscheidung bezüglich GRIAT getroffen ist. 
Wenn wir entscheiden, aus den Programm auszusteigen, müssen wir trotzdem die Betreuung der bereit eingeschriebene Studierende weiterführen.   

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