I am not sure whether I understand your problem in the right way. The cycle time of a non-pipelined processors is assumed there (naively) as Delta := p * delta where p is the number of pipeline stages and delta is the cycle time of the pipelined processor. Since p is not 1, the two are different, and that is also the case in reality since the pipeline stages are circuits with a much shorter critical path. Hence, the pipelined processor will have a higher clock frequency.
In the second half of slide 93, we assumed Delta := p * delta which allowed us to cancel out delta to estimate the speedup as roughly p. But the following slides shown that this is a too optimistic assumption and that the reality will be less than p.