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Can someone explain to ùe the examples of cache hits and misses in the ubungblatter?

Sometimes there are misses/hits on ldi and sometimes not.
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Whether there is a hit or a miss for an instruction depends on the history of the former load/store instructions, i.e., whether these have loaded the memory block in question into the cache or whether they have loaded another one at the same place so that the once loaded block has been evicted.

Therefore, you cannot say for one load/store instruction in the program whether it has a hit or miss, you can just say that for a particular execution of such an instruction: If the instruction is executed within a loop, it may be the case that every second execution is a hit or a miss (see e.g. the solutions of problems 2 of the exam papers of 2015).  See also https://q2a.cs.uni-kl.de/2264/frage-zur-altklausur-von-2017-zur-aufgabe-2c.
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