Datenkonflikte | dataconflicts

Question

I have a qustion regarding data conflicts.

To be honest i am a little bit confused by one solution in the 2017 exam.

Taking a look at the drawn in conflicts, it becomes quite clear that only conflicts that could acctually happen on a given processor (doe to the piline architecture) are drawn in (otherwise  RAW: 2-> 7).

Quite obviosly this programm is executued on a processor without register bypassing(RAW: 0->3).

So far so good.

The things i dont understand are the WAW and WAR conflicts.

Since we only write registers in WB, WAW and WAR conflicts could never occure or am i wrong ?

This task propably uses a different processor right ?

Or are simply not all conflicts drwan in ? 

And I have two more unrealted questions.

In the exam, could it happen that we need to draw the scoreboard ?

And lastly, should we report all mistakes in the solutions \ exams ?

i found a handfull of them :

e.g. : 2017  Task 2 a : A4  Tag should be 7 insted of 6

2015 exam . in one grammar the the tuple sais that the start sybol is E but througout the hole solution A is used as the start symbol (i guess because it is the first production rule )

I foud a few more, but i cant remember them of hand =)

I hope you can help me

Thanks in advance

Comments

Thanks for pointing out the mistakes in the sample solutions of the exam papers. They should now be fixed.

Answer 1

I agree that the solution seems to be broken. I also saw that some of the example solutions were not correct (they have been made long after the exam at some time, and were made in a hurry). Please forward the mistakes you found to us.

About your questions: The problem was actually asking for the conflicts that can happen in a program, and not in a particular processor pipeline (which would have to be specified otherwise). Because of this, the WAW and WAR conflicts do make sense. 

In general, we should either (1) ask for all conflicts in the program (regardless of any particular processor pipeline) or (2) ask for conflicts in a particular pipeline (and then that pipeline must be specified precisely). Anything in between does not make sense. 

The program has however a particular problem: instructions 6 and 7 are not reachable and can therefore not have conflicts to any other instruction. I therefore see the following data conflicts:

• RAW: (0 → 2), (1 → 2), (0 → 3), (2 → 4), (3 → 4)
• WAW: (1 → 2), (2 → 8)
• WAR: (4 → 8)

The solution has been updated accordingly. 

I guess that we will not ask you for the scoreboard. It is nothing else than remembering which registers will be updated by the instructions that are currently in the pipeline, and that is something you also will have to handle when we ask for the pipeline conflicts.

Comments

Tanks allot for your help.
I get the same results for this exercise, so i guess i can be relieved now;)

I'm not entirely sure how to forward errors to you (which email i should use).
One error came back to my mind this morning.
In the 2015 solution task 2, were supposed to calculate again the necessary tag length.
The Hits in the solution of task 2c) imply that we have 2 words per block and therefore a word size of 1Byte.  Since our main memory has a size of 512 Bytes, I get the following results:
 =>log2(512/1)=9   =>
Cache    sätze    Blöcke/Satz    #tag    #index    #word-offset
DM             8            1                    5      3             1
A2             4            2                    6      2             1

If the word size would by 2 bytes, I get this solution:
=>log2(256)=8   =>
Cache    sätze    Blöcke/Satz    #tag    #index    #word-offset
DM            8            1                     5    3            0
A2            4            2                     6    2            0