Sure, you just have to look at the binary representation of the addresses, and have to split them into the tag, the set address and the block offset. Instead of this partitioning of the addresses, you may also work with div and mod operations, but since the binary addresses were already in the table of that exam problem, it is easier to partition the binary addresses.
Since a block has two bytes in that exercise, you need the rightmost bit for the block offset, and the next three bits determine the set address (since the cache has 8 blocks). The rest is the tag.
Maybe you are asking how to determine the memory addresses accessed by the load/store instructions. That can not be answered in general, you really have to have a look at the assembler program and have to understand what it does. In that program, you can see that $2 is incremented in each loop iteration, and $3 is $2 modulo 4. Based on this, you get the addresses.
