MESI Cache Coherence Protocol

Question

In this example we have tried executing the MESI protocol from the exam of September 2019. While comparing with the solutions provided on the website we noticed that our solution is off in one line.

In line 8 CPU[0] loads from mem. address 4. Since address 4 is in block address 2, we know that CPU[1] has to write its modified values back to memory. Now in our solution CPU[0] additionally reads block 2 from memory, but in the provided solutions it doesn't.

Since the solutions do not claim to be complete I'm now unsure: Was this read from memory simply omitted in the solutions or is there something we have overlooked when studying the protocol?

Answer 1

In line 8, CPU[0] executes instruction load(4) which means to load block(2) which is currently held in the cache of CPU[1] in state modified. So, what needs to happen is that (see slide 34, case 2)

1. the block is written back to the main memory by CPU[1]
2. the block is copied to the cache of CPU[0]
3. the block is kept in the cache of CPU[1] (since CPU[0] issued a load instruction instead of a write)

To this end, CPU[1] has to write back block(2) to main memory, and to this end the content of block(2) is put on the memory bus together with its block address. At this time, both the main memory as well as CPU[0] grab the content of block(2) from the bus, so that the above steps 1 and 2 happen at once. 

So, the solution given in the exam is correct and has this reasoning, but yours would also be fine, in my opinion, since it describes even in more detail what is going on. However, the two block transfers 1 and 2 above can be done during one memory bus transaction which saves time.