For the 256 bytes, we need 8-bit addresses. The caches have 32 bytes and a block has 2 bytes, so that each cache has 16 blocks.

The direct mapped cache therefore needs 4 bits for set addresses so that a memory address a[7..0] is split into the tag a[7..5], the set address a[4..1] and the block offset a[0]. The set address a[4..1] is therefore computed as setAdr(adr) := (adr % 32) div 2. We therefore have

- setAdr(30) = 15
- setAdr(31) = 15
- setAdr(32) = 0
- setAdr(33) = 0

Hence, the set address is 0 and not 16 as you assumed.

For the 4-way set associative cache, we have 4 blocks in a set and therefore each set has 8 bytes, so that the cache has only 4 sets. To that end, we need 2 bits as set addresses, so that a memory address a[7..0] is split into the tag a[7..3], the set address a[2..1] and the block offset a[0]. The set address a[2..1] is therefore computed as setAdr(adr) := (adr % 8) div 2.