The slide shows a pipeline with p pipeline stages numbers as 1..p where instructions enter at stage 1 and are then processed by the stages until they leave the pipeline at stage p. As we consider a stream of instructions I(0),I(1),I(2),... executed by the processor, we look at some time t at the pipeline and find there the following instructions:
We don't know much about this general pipeline, so at any stage the instruction may read and write certain memory locations (registers). Writing may furthermore be done with or without a delay (using register bypassing or not).
Now we consider the instruction at some stage i which is above the instruction I(t). Instruction I(t) has a RAW conflict to one of its preceeding instructions I(t-1),...,I(t+i-p) which are still in execution in case I(t) reads now, i.e., in stage i, some memory location that will be written by one of the instructions I(t-1),...,I(t+i-p) while they continue their way through the pipeline.
To be more precise, immediate writes of the instructions I(t-1),...,I(t+i-p) at that point of time are okay (since these are already read by I(t) in stage i or can at least be forwarded), but delayed writes at that point of time of the instructions I(t-1),...,I(t+i-p) are already too late. Also later writes, regardless whether with or without delay of the instructions I(t-1),...,I(t+i-p) are too late, since I(t) has already done a read which was too early. Note that in a sequential execution, I(t) will read what has been written by I(t-1),...,I(t+i-p) before (since all of those writes are done before I(t) is executed).
The situation is explained in more detail in the slides that follow, but it is admittely, not that easy to express.