When caches are used, we use the cache as a replacement of certain blocks of the main memory. In any case, we first have to transfer a block from the main memory to the cache, and when reading it, there is still nothing to be discussed. However, when writing a word of such a block, we clearly need to change the block in the cache. Concerning the update of the corresponding block in the main memory, we have however two major choices:
- With a write-through strategy, we would also update the block in main memory so that it will be always consistent with the cache block.
- With the write-back strategy, we avoid this, but remember that the block in the cache is now "dirty" which means that it has been modified and is no longer the same as the corresponding one in the main memory.
When a cache block has to be removed from the cache (since another block needs that space), we can simply drop that cache block when using a write-through strategy, but need to write it back to the main memory in case it is dirty and a write-back strategy is used.
Write-back strategies are mainly used since they make full use of the speed of the caches (recall that write-through requires to also write the block to the main memory so that the caches have no real advantage apart from being able to contine while the memory write is not yet done). Write-back strategies are however slightly more complicated to implement since we have to maintain a dirty flag of the cache blocks that tells us whether writing the block back to main memory is required or not (recall that writing to memory is slow and we want to avoid that as much as possible by the use of caches).
To avoid confusion: There are write strategies of caches like "write-back" and "write-through", but we also speak of "writing back a cache block to main memory" in both cases. The latter has to be done in any case (of modified blocks), but the point of time when that is done is different with the strategies "write-back" and "write-through". Also, please distinguish it from the "write-back" stage of processor pipelines where usually result values are written into the registers.
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