The immediate operand for these instructions denotes the number of shifts. For instance, SLL rd,rt,sa will take the register Reg[rt] with content x..x and will assign x[31-sa]..x0...0 to register Reg[rd]. Hence, register Reg[rt] is shifted by sa bits to the left (the leftmost sa bits are lost), and sa zero bits are concatenated to the right hand side. This is a logical shift while arithmetical shifts SRA rd,rt,sa will assign x[31-sa]..xx..x[32-sa].
Having immediate operands, these are I-type instructions.