# Why do R-Type Register have shamt-Bits in MIPS?

Why do R-Type Register have shamt-Bits in MIPS?

If I have gotten it right, in MIPS the instructions SLL, SRA, ans SRL are I-Type Instructions. Thus, sa is a constant. I dont understand what the shamt-Bits are for. Is the result shifted by its value?

Thank to all answers!

+1 vote

I believe the shift instructions (SRL,SLL ...) are categorized as R-type instructions in MIPS. So the constant that appears in these instructions (i.e. the shift amount) is in the shamt field of R-type instruction format, which contains 5 bits. Only 5 bits (values 0 to 31) are sufficient to represent the shift amount for these instructions. On other hand, the constant in I-type instructions occupies 16 bits. So I believe that is used to hold a full fledged operand. Right ?

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The immediate operand for these instructions denotes the number of shifts. For instance, SLL rd,rt,sa will take the register Reg[rt] with content x[31]..x[0] and will assign x[31-sa]..x[0]0...0 to register Reg[rd]. Hence, register Reg[rt] is shifted by sa bits to the left (the leftmost sa bits are lost), and sa zero bits are concatenated to the right hand side. This is a logical shift while arithmetical shifts SRA rd,rt,sa will assign x[31-sa]..x[0]x[31]..x[32-sa].

Having immediate operands, these are I-type instructions.
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